AMC 20-193 & CAST-32A / Multi-Core Processing Training
Course Schedules Here
SYNOPSIS:
CAST-32A is the worldwide (America, Europe, Asia) Certification Authorities Software Team (CAST) guidance for ensuring safe implementation of Multi-Core Processing (MCP) within avionics systems. Increasingly MCP’s are used in avionics and understanding what must be done to plan for, implement, and verify deterministic “safe” MCP development via CAST-32A is the focus of this AFuzion 2-day private training course. Attendees will understand how to utilize multiple-cores providing simultaneous operations using deterministically shared resources such as cache, memory, and communications and performing MCP CAST-32A Interference Analysis. Attendees will also learn how to work with RTOS vendors and RTOS’s themselves to comply with CAST-32A and develop safer avionics.
AC 20-193 replaces CAST-32A and provides added details for certification “guidance” (rules!) when using two more cores (if only one core is used/activated, and you can prove such, then neither CAST-32A or AC 20-193 is applicable). Clearly multicore processing is the future of avionics for increased throughput and scalability/reusability. But using two or more MCP cores implies near-mandatory sharing of MCP resources including memory, cache, communications, etc. In almost all cases, a multicore certified RTOS is required to assist in ensuring deterministic resource management; this means the RTOS itself is certifiable to both DO-178C and AC 20-193, with AFuzion’s training tailored to include RTOS specifics as needed by your training attendees.
MCP processors enable vastly greater processing but can also include additional drivers, embedded security, advanced graphics processing, and memory management. These MCPs provide many benefits but their operation requires additional design and verification considerations due to “interference channels”, where interference as described above (communications, memory, cache, etc.) must be understood with defined mitigations in place.
This AFuzion MCP AC 20-193 training specifically addresses Interference and Determinism to help ensure you can provide certification evidence proving that interference between cores is fully understood and managed both at your architecture level and operational level. Attendees will understand the relationship between AC 20-193 and DO-178C for software and DO-254/A(M)C 20-152A for hardware.
AMC 20-193 (AC 20-193 per FAA) is the new replacement for CAST-32A handling Multi-Core Processing (MCP) development and certification; AFuzion’s MCP training has now added coverage for A(M)C 20-193 per EASA, FAA, and worldwide Military adoption. AFuzion is additionally the sole MCP Certification training and auditing/mentoring resource for USA and European militaries.
AFuzion’s training has been provided to over 23,000 aviation engineers from 1,000 companies in 30 countries; more than all other trainers in the world combined. Brief summary below; contact us for more free information.
KEY FEATURES:
- CAST-32A & AC 20-193 Introduction
- Summary of DO-178C, for Multi-Core usage
- Interference Channels per AC 20-193
- RTOS Introduction & Scheduling, Processes, Tasks, and Threads
- MCP What & Why
- DO-178C & MCP – Plans, Standards, Activities
- AC 20-193 MCP Robust Partitioning Principles
- RTOS Specifics – Technical Info
- DO-254 & MCP
- MCP Cert, Deadlines, Benchmarks & Reports
- Overview: IMA, ARP4754A, ARP4761 & MCP
- IMA & AC 20-193 Modules and Partitioning
- DO-178C’s & MCP Requirements, Design & Verification
- MCP & AC 20-193 Best Practices for Planning, Testing, & Certification
- MCP & AC 20-193 WCET Mistakes & Best Practices
WHO:
Attendees may include software engineers and managers. Basic understanding of embedded systems and software is helpful (introductory DO-178C and RTOS’s will be provided early in Day 1).
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Request Free AMC 20-193 & CAST-32A Training Info and Free Whitepaper